Revisions: IC660ELB931A , IC660ELB931B , IC660ELB931C , IC660ELB931D , IC660ELB931E , IC660ELB931F , IC660ELB931G , IC660ELB931H , IC660ELB931I , IC660ELB931J , IC660ELB931K , IC660ELB931L , IC660ELB931M , IC660ELB931N , IC660ELB931O , IC660ELB931P , IC660ELB931Q , IC660ELB931R , IC660ELB931S , IC660ELB931T , IC660ELB931U , IC660ELB931V , IC660ELB931W , IC660ELB931X , IC660ELB931Y , IC660ELB931Z ,
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low voltage/Host RESET detect This input monitors the output of a bi-stable latch controlled by the voltage detection circuit and the Host system RESETDRV line. It goes low and stays low (until reset) whenever the voltage on the motherboard drops below 3.12 volts or the system RESETDRV line goes high, indicating the Host system has gone into RESET. The latch controlling this line is reset by the 1 bit of Port B. During normal operation this line should stay high (logic 1). 1 - watchdog timer status This line is high while the watchdog timer is enabled (by jumper JP2) and being pulsed every 727 ms by output 0 of Port B. If the timer times out, this line goes low (logic 0). It will go low if either the voltage detector detects a low voltage or the system RESETDRV line goes high and the timer times out. The timer will time out if not pulsed every 727 ms (with jumper JP2 in the 2-3/Enabled posit ion). 2 - interrupt request When the daughterboard generates an interrupt to the motherboard, this line goes high (logic 1) and stays high until reset by output 2 of Port B. The bi-stable latch that stores this interrupt is edge triggered. 3 - PClM OK signal The state of this line follows the condition of the PClM OK LED on the daughterboard. If the LED is lit, the PClM OK signal into the PPI is low (logic 0). 4 - COMM (communications) OK signal Like the BOARD OK signal above, this signal also follows the output of one of the LEDs on the daughterboard. This line into the PPI is low (logic 0) if the COMM OK LED on the daughterboard is lit. 5 - NC 6 - N C 7 - N C Getting Star-ted 3-9 - Port B: 0 - watchdog timer pulse signal If the watchdog timer is enabled by jumper JP22, this line should be pulsed at least every 727 ms in order to keep the watchdog timer timing. The timer is triggered on the rising edge of the signal, so it is necessary for you to program the PPI to provide a low to high transition on this signal line. This line must be pulsed at least once to allow the daughterboard to come out of RESET. 1 - clear RESET request When the system RESETDRV signal goes high indicating a system RESET, or when the voltage detector on the motherboard detects a Iow voltage condition, a bi-stable latch is set that drives the motherboard RESET circuit. The output of this latch can be read on bit 0 of Port A on the PPI (see above). This line (bit 1 of Port B) clears the latch when lowered (logic O), and when raised again (logic 1), readies the latch for the next detection of RESET or low voltage condition. 2 - clear interrupt request This line is used to clear the interrupt request bi-stable latch on the motherboard after an interrupt has been received from the daughterboard. Bringing the line logic 0 clears the latch and then back to logic 1 prepares it for the next interrupt. As long as this line is low, the latch will not latch incoming interrupt requests. 3 - HHM test An HHM present can be indicated even when one isn t plugged in by raising this line to a logic 1. After power up and under normal conditions, lower (logic 0) this line and leave it low. 4 - factory test This line should not be used and should be left low (logic 0) all the time. 5 - interrupt output (to the daughterboard) This output from Port B drives the GENINT/ interrupt line to the PCIM connector. When pulsed low (logic 0) it requests an interrupt from the daughterboard. Not operational for the PCIM - should be logic 0. 6 - PCIM RESET When this line is low (logic 0) it pulls the PCIM into RESET. Under normal conditions, it should be left high. 7-NC 3-l 0 Getting Started GFK-0074 Application Example To set up the PCIM, first set up the PPI. The PPI is initialized by defining ports A and C as input ports and port B as an output port. In BASIC, this statement would suffice: 100 OUT 959,153 This example statement writes a value of 153 decimal (99 hex) to the control byte of the PPI located in I/O memory at location 995 decimal, or 3E0 hex. For the purposes of this example, assume the dip switches have been set to respond to the I/O address range of 992 hex through 995 hex. The value of 99 hex causes ports A and C to be configured as inputs and port B as an output port. Port B is now an output port and all eight of its outputs are high - they shouldn t be left that way for long. Lines D1, D2, D3, D6 and D7 of port B should be lowered to prevent any interrupts to the Host system and make sure the PCIM is in RESET, always a good place to start. The BASIC statement to perform this is: 110 OUT 993,01 This statement writes a 1 decimal (1 hex) value to Port B byte. Then, to bring the PClM out of RESET, execute the following statement: 120 OUT 993,67 This raises D1 and D6, and allows the PCIM daughterboard to run in the memory space determined by the dip switch settings. That is: nnn OUT Base t 3, 99h nnn OUT Base t 1, l nnn OUT Base t 1, 43h In Microsoft C compiler, the library function outp (port, value) is used, Try coding the values shown in the Basic example above in the following in Microsoft C statements to set ON the PCIM: |
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